EDN

Delay- and phase-locked loops becoming reusable IP

San Mateo, Calif. – Phase-locked and delay-locked loops are becoming increasingly important weapons in the system-on-chip design arsenal, but PLLs and DLLs are notorious for their difficulty. Now, ...
Nature

Delay-Locked Loop Design and Applications

Delay-locked loops (DLLs) are critical components in modern electronic systems, providing robust synchronisation of clock signals in a variety of applications ranging from high-speed communication to ...
Ars Technica

Delay Locked Loop command and some scary binary.

I figured this was the best place to post up about this as it is about settings GDDR3 mode register commands.<br><br>So, The card I have is a 7600GT. Let me go through what exactly i have ...
Design-Reuse

True Circuits Introduces Delay-Locked Loop Hard Macros

Silicon Proven Low-Jitter DLLs Target High-Speed DDR Style Interface Applications LOS ALTOS, California, October 8, 2003 - True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal ...
GPS World

Expert Advice: Quasi-Coherent Delay Lock Loop Tracking and Generalized Binary Coded Symbols in Multipath

The original GPS signals, and indeed most GPS signals including L5, utilize conventional pseudonoise (PN) signal code division multiple access (CDMA), some with both in-phase and quadrature-phase ...
EDN

Agreement to Dismiss Claims Regarding Delay Locked Loop Patent

MOSAID Technologies Incorporated announced that it has filed a proposed Stipulated Order of Dismissal for all infringement claims with respect to U.S. Patent No. 6,067,272 (the “DLL patent”) covering ...