The first article in this series titled “The common silicon issues in analog IP integration” focused on system-on-chip (SoC) design issues related to incorporating analog IP. Here we begin expanding ...

The previous articles in this series showed how the successful integration of IP—especially analog/RF, but digital as well—is essentially pre-determined by the practices of the chip development team ...

Nvidia Corporation is set to implement a new advanced packaging technology called Chip-on-Wafer-on-Platform PCB (CoWoP) for its next-generation GR150 AI GPU, expected to launch in 2027. This approach ...

Advanced packaging techniques are viewed as either a replacement for Moore’s Law scaling, or a way of augmenting it. But there is a big gap between the extensive work done to prove these devices can ...

This file type includes high resolution graphics and schematics when applicable. In the development of SoC-based (system-on-chip) circuit boards, the SoC’s additional capabilities will provide ...

As the AI and HPC markets develop, high-performance computing is rapidly growing, driving the demand for high-speed transmission. Naturally, the complexity of chip design has also increased ...

Cadence Design Systems has started bringing artificial intelligence (AI) into the fold on its flagship chip design suite to help designers build smaller, faster processors that consume less power and ...